The present invention relates to magnetic memory systems, and more particularly to a method and system for providing a magnetic memory and a read/write scheme for utilizing the magnetic memory.
Magnetic memories are often used in storing data. One type of memory currently of interest utilizes magnetic tunneling junctions in the memory cells. A magnetic tunneling junction typically includes two ferromagnetic layers separated by a thin insulating layer. The insulating layer is thin enough to allow charge carriers to tunnel between the ferromagnetic layers. The resistance of the magnetic tunneling junction depends upon the orientation of the magnetic tunneling junctions.
FIG. 1 depicts a conventional magnetic memory cell 10 as used in a conventional magnetic memory. The conventional memory cell 10 is coupled with a bit line 20 and receives a current Ir 18 during reading. The conventional memory cell 10 includes a magnetic tunneling junction 12 and a transistor 14. The magnetic tunneling junction 12 is represented by a resistor. The magnetic tunneling junction 12 is coupled to the drain of the transistor 14. The source of the transistor 14 is coupled to ground. The state of the magnetic tunneling junction 12, and thus the data stored by the conventional memory cell 10 is sensed by detecting the voltage at output 16. The output 16 is coupled to the magnetic tunneling junction 12 of the conventional memory cell 10.
Also depicted in FIG. 1 are the conventional word line 22 and conventional digit line 24. The conventional word line 22 is used to select a row of memory cells during reading. Simultaneous use of the bit line 20 drives a read current through the selected memory cell 10. During writing, the conventional digit line 24 and the bit line 20 carry the current used to write data to the selected memory cell 10.
FIG. 2 depicts a conventional memory array 30 using the conventional memory cell 10. The conventional array 30 is shown as including four conventional memory cells 10. The memory cells 10 are coupled to reading/writing column selection 32 via bit lines 34 and 36 and to row selection 50 via conventional word lines 52 and 54. The bit lines are coupled to the magnetic tunneling junctions 12, while the conventional word lines 52 and 54 are coupled to the gates of the transistors 14. Also depicted are conventional digit lines 44 and 46 which carry current that applies a field to the appropriate conventional memory cells 10 during writing. The reading/writing column selection 32 is coupled to write current source 38 and read current source 40 which are coupled to a line 42 coupled to a supply voltage VDD 48. Also shown are current source Iw 38 and Ir 40 used in writing and reading, respectively, to the conventional memory cells 10. Also depicted are transistors 58 and 60 that are controlled using control line 62. FIG. 2 also depicts reference cells 10xe2x80x2, reference current 64 and reference signal output 66. The reference current 64 is typically the same as the read current 40.
FIG. 3 depicts a cross-section of the conventional memory array 30. Memory cells 10 having magnetic tunneling junctions 12 and transistors 14 are depicted. The free layer 11, tunneling barrier 13 and pinned layer 15 of each magnetic tunneling junction 12 are shown. The gate 17, drain 19 and source 21 of the transistor 14 and the connection 23 between the between the magnetic tunneling junction 12 and transistor 14 are also explicitly shown. Also depicted are the corresponding conventional word lines 52 and 54, conventional digit lines 44 and 46 and bit line 34.
Referring to FIGS. 1, 2 and 3, in order to write to the conventional memory cell 10, the write current Iw 38 is applied to the bit line 34 or 36 selected by the writing/reading column selection 32. The read current Ir 40 is not applied. Both conventional word lines 52 and 54 are disabled. The transistors 14 in all memory cells are disabled. In addition, one of the conventional digit lines 44 or 46 selected carries a current used to write to the selected conventional memory cell 10. The combination of the current in a conventional digit line 44 or 46 and the current in a bit line 34 or 36 will write to the desired conventional memory cell 10. Depending upon the data written to the conventional memory cell 10, the magnetic tunneling junction will have a high resistance or a low resistance.
When reading from a conventional cell 10 in the conventional memory array 30, the write current Iw 38 is disabled and the transistors 58 and 60 are turned off by controlling the control signal through the control line 62. The read current Ir 40 is applied instead. In addition, the reference current 64 is applied to reference cells 10xe2x80x2. The memory cell 10 selected to be read is determined by the row selection and column selection 32. The transistors 14 in the selected cell are on. The output voltage is read at the output line 56 and compared to the reference signal at the reference signal output line 66.
Although the conventional memory array 30 and the conventional memory cells 10 function, one of ordinary skill in the art will readily recognize that the conventional memory array 30 is limited in density and relatively difficult to fabricate. The conventional word lines 22, 52 and 54 are electrically isolated from the conventional digit lines 24, 44 and 46. Moreover, as depicted in FIG. 3, the conventional word lines 22, 52 and 54 are typically under the digit lines 24, 44 and 46, respectively. Consequently, the conventional memory array 30 requires more space vertically. The conventional memory array 30 thus has a greater dimension laterally for a given number of cells. Furthermore, additional processing is required to fabricate and adequately insulate the conventional word lines 22, 52 and 56 as well as the conventional digit lines 24, 44, and 46. Because of the difficulty in processing and greater space requirements, increasing the density of the conventional memory array 30 and decreasing the minimum width and feature size of the conventional memory array 30 are difficult.
Accordingly, what is needed is a system and method for providing a magnetic memory cell allowing for an increased density. The present invention addresses such a need.
The present invention provides a method and system for providing and using a magnetic memory including magnetic memory cells. The method and system include providing a magnetic tunneling junction including a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The magnetic memory cell is coupled to a merged word line and a bit line. The merged word line selects the magnetic memory cell during a reading and carries a write current for the magnetic memory cell during writing. The bit line provides current to the magnetic memory cell during the reading and the writing. The currents provided by the bit line and the merged word line during writing allow data to be written to the magnetic memory cell.
According to the system and method disclosed herein, the present invention provides a magnetic memory capable of having higher density and that is simpler to fabricate.